1. Field of the Invention
The present invention relates to a data processor, and in particular, to a serial data processor having a clock line and a data line, which executes the transmission/reception of data in synchronism with a serial clock.
2. Description of Related Art
As a way for transferring data between a plurality of semiconductor processors (called "LSI" hereinafter) there are provided a means a method using a data bus of 8 bits or more, parallel lines and a serial transfer method transferring the data in series bit by bit. Since the latter method requires a fewer number of signal lines for connecting the LSIs to one another, it is largely used as a simple data transfer means between LSIs.
In serial data transfer, one unit of data (for example, of 8 bits) is transferred continuously in the form of serial bits, but an interval period is required between transfers of each unit of data to confirm the reception. If the receiver is not capable of receiving data, it is necessary to wait until the receiver becomes capable. Conventionally, in the case of a receiver which is capable, a BUSY signal is supplied to the transmitter. The transmitter checks the BUSY signal and discriminates whether or not the data can be transferred so as to generated a transfer start signal when it becomes possible to transfer. This start signal is needed in order to control a serial clock necessary for serial data transfer or to clear a counter counting the bit number of data to be transferred.
However, the conventional serial data processor has been so designated that after checking whether or not the processor which is to be a receiver is in a busy condition, a start signal for the next data transfer is not generated until the busy condition is dissolved. Thus, in case the busy condition extends for a long time, the useless waiting time for checking the busy condition is increased, lowering the efficiency of the whole data processing operation. Specifically, in the serial data processor the simplest way to check the busy condition by is interrupt processing. However, in a data processor which does not perform the function of multi-interrupt control, if another interrupt is generated during the checking time, the processing of the second interrupt must be waited delayed until it is returned to the main program after dissolution of the busy condition. Thus, there has been a problem in that it takes an extremely long time to respond to the interrupt. Further, it is necessary to prepare a program for maintaining the data processor in a waiting condition until the busy condition is dissolved, thereby limiting the program area for the proper processing of data.
On the other hand, a serial data processor which is used as a receiver,after having received serial data, outputs a BUSY signal so as to inform another serial data processor which is used as a transmitter that the receiving device is in the course of processing data processing. Therefore, it has been required to execute special programs for setting and dissolving the BUSY signal. Such programs are mostly started by interrupt processing. Since it must take a long time to execute interrupt processing for the BUSY control, a long period is required until the data processor returns to the proper main program processing after reception of the serial data. Further, as it is necessary to prepare the programs for setting and dissolving the BUSY condition, there has been a problem in that the program area for proper data processing is limited by the programs for controlling the BUSY signal. Particularly, in case a large amount of data is transferred in series, one round of processing consisting of a 1-bite serial data transfer and data processing needs a long time. Thus, there also is the drawback that the transfer speed is lowered.